Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Permutation and phase independent Boolean comparison
Integration, the VLSI Journal
Limits of using signatures for permutation independent Boolean comparison
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Logic Matrices and the Truth Function Problem
Journal of the ACM (JACM)
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Efficent Boolean Matching Algorithm for Cell Libraries
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
Exploiting structure in symmetry detection for CNF
Proceedings of the 41st annual Design Automation Conference
Efficient computation of canonical form for Boolean matching in large libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
Efficient canonical form for Boolean matching of complex functions in large libraries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Boolean Matching with Don't Cares
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A unified approach to canonical form-based Boolean matching
Proceedings of the 44th annual Design Automation Conference
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Faster symmetry discovery using sparsity of symmetries
Proceedings of the 45th annual Design Automation Conference
FPGA technology mapping with encoded libraries andstaged priority cuts
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
Automatic Discovery of Transition Symmetry in Multithreaded Programs Using Dynamic Analysis
Proceedings of the 16th International SPIN Workshop on Model Checking Software
Design and synthesis of programmable logic block with mixed LUT and macrogate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A transform-parametric approach to Boolean matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Building a faster boolean matcher using bloom filter
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the Conference on Design, Automation and Test in Europe
Integrated logic synthesis using simulated annealing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the International Conference on Computer-Aided Design
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Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Boolean matching is the computation of a canonical form to represent functions that are equivalent under negation and permutation of inputs and outputs. In this paper, we first present a detailed analysis of previous techniques for Boolean matching. We then describe a novel combination of existing methods and new ideas that results in a matcher which is dramatically faster than previous work. We point out that the presented algorithm is equally relevant for detecting generalized functional symmetries, which has broad applications in logic optimization and verification.