Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Improving the accuracy of circuit activity measurement
DAC '94 Proceedings of the 31st annual Design Automation Conference
Switching activity analysis using Boolean approximation method
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Switching activity analysis for sequential circuits using Boolean approximation method
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Effects of correlations on accuracy of power analysis—an experimental study
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient switching activity simulation under a real delay model using a bitparallel approach
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Stochastic sequential machine synthesis with application to constrained sequence generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Power Estimation of Large Circuits
IEEE Design & Test
Estimating Circuit Activity in Combinational CMOS Digital Circuits
IEEE Design & Test
A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Power Estimation Under Uncertain Delays
Integrated Computer-Aided Engineering
Switching activity models for power estimation in FPGA multipliers
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient statistical approach to estimate power considering uncertain properties of primary inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.