Discrete-time signal processing
Discrete-time signal processing
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Estimation of circuit activity considering signal correlations and simultaneous switching
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A cell-based power estimation in CMOS combinational circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Low power synthesis of sum-of-products computation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
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In this paper, we propose a method for power optimization of digitalsignal processing (DSP) systems through reduction of circuit switchingactivity estimated from high levels in the synthesis hierarchy, namely atnumerical and algorithmic levels. The optimization involves application ofa numerical transformation called number-splitting on the systemcharacteristic coefficients. The transformation alters the systemcharacteristic coefficients while preserving the input/output relations. Foreach set of candidate coefficients, the corresponding signal flow-graph isconstructed for evaluation of power consumption. First, the switchingactivity at all computation nodes of the graph are estimated using our novelactivity transformation models, which quickly estimate the activity atthe output of the adders and multipliers based on the activity at theinputs. Next, the activity at the inputs of each computation node are usedto compute the average power consumption by that node, using our heuristicpower estimators.The optimization framework can be applied to hardware-dedicatedbit-serial, nibble-serial, as well as programmable word-parallelarchitectures. We focus on hardware-dedicated bit-serial systems, and showthat up to 35 percent savings in power is achievable.