Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Peak power estimation of VLSI circuits: new peak power measures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exact and approximate estimation for maximum instantaneous current of CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with the accuracy of low-level power simulation. We rely on efficient RT-level peak power prediction heuristics to select a handful of input vector pairs from the simulation testbench. These vector pairs are highly likely to induce the worst-case peak power. After that, the low-level power simulation is performed only with these peak power candidate vector pairs to obtain the realistic peak power values. Computationally, there are three major stages in our methodology. Firstly, we analyze the structure of the circuit and calculate the peak power weight for each input pin so as to construct a so-called mountain-based model. Secondly, we perform waveform composition to compute the peak power metric for each given input vector pair. Finally, we select a few candidate vectors for low-level power simulation. By doing so, the time-consuming simulation at the low levels can be mostly avoided without losing accuracy. Experiment results show that only less than 1% of the total functional patterns defined in a testbench are needed to be selected for low-level power simulation in order to catch the worst-case peak power vector pair.