Minimal area sizing of power and ground nets for VLSI circuits
Proceedings of the fourth MIT conference on Advanced research in VLSI
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Estimation for maximum instantaneous current through supply lines for CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power estimation starategies for a low-power security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
RT-level vector selection for realistic peak power simulation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
Sleep transistor sizing for leakage power minimization considering charge balancing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing for leakage power minimization considering temporal correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Both the IR drop and EM problems require accurate analysis of maximum instantaneous current (MIC) on the power supply bus. We propose a vectorless approach to deriving a tight upper bound on MIC. We first characterize different types of signal correlation which may cause the MIC estimation to lose accuracy. We next propose theorems to identify gates which switch mutually exclusively, taking into account correlation across sequential elements (flip-flops). Note that previous research of this topic addressed on combinational circuits only. After obtaining the information of mutually exclusive switching, we then apply a graph algorithm to obtain an upper bound on MIC. In average, our results on sequential benchmarks are 212% tighter than those from iMax and 129% tighter than those from PIE based on H. Kriplani et al. (1995).