A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Probabilistic analysis of large finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A novel methodology for transistor-level power estimation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exact and approximate estimation for maximum instantaneous current of CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A network security processor design based on an integrated SOC design and test platform
Proceedings of the 43rd annual Design Automation Conference
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In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the logic part, we present a highly accurate tool, called PowerMixer. This tool is a refinement of the so-called mixed-level methodology that combines the accuracy of quick SPICE and the speed of gate-level simulation. A grouping scheme is proposed so as to improve the accuracy for design blocks as large as 100K gates. For the memory part, we investigated the power consuming behavior of memories and point out the potential problems associated with the current commercial design flow. These tools, along with a previously published static peak power estimation method [4], jointly provide an evaluation platform for the power optimization and verification process of our security processor in a practical way.