Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hierarchical electromigration reliability diagnosis for VLSI interconnects
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Maximum power estimation using the limiting distributions of extreme order statistics
DAC '98 Proceedings of the 35th annual Design Automation Conference
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A static estimation technique of power sensitivity in logic circuits
Proceedings of the 38th annual Design Automation Conference
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A vectorless estimation of maximum instantaneous current for sequential circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Satisfiability models for maximum transition power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
In combinational logic circuits, a single switching event on the primary inputs may give rise to multiple switchings at the internal nodes. This glitching effect is caused primarily by unequal delay paths and results in increased power consumption and decreased device reliability. In this paper, we present a new algorithm to estimate the maximum number of transitions at internal nodes in combinational CMOS VLSI circuits. Unlike exhaustive simulation, our algorithm is based on the technique of propagating uncertainty waveforms throughout the circuit and using these waveforms to count the maximum switching activity at every node. Our approach guarantees a tight upper bound on the number of transitions which is necessary to assess the minimum circuit reliability lifetime and maximum power dissipation.