Pareto-optimal hardware for digital circuits using SPEA

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil;Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Brazil
Venue:
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Year:
2005

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Abstract

In this paper, we focus on engineering Pareto-optimal digital circuits given the expected input/output behaviour with a minimal design effort. The design objectives to be minimised are: hardware area, response time and power consumption. We do so using the Strength Pareto Evolutionary Algorithms. The performance and the quality of the circuit evolved for some benchmarks are presented then compared to those of single objective genetic algorithms as well as to the circuits obtained by human designers.