Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Register placement for low power clock network
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose an event-driven simulation based approach to estimate the worst case IR drop and Ldi/dt inductive noise on the power supply network. The switching noise is modeled as a weighted sum of the switching currents and the rates of change of the switching currents, where the weights are respectively the effective resistance and inductance (on the P/G network) experienced by each switching current. Monte Carlo and Genetic Algorithm are employed to search for the worst-case input vector pair(s) that induces the maximum switching noise. The worst-case input patterns are used in the SPICE simulation to verify the switching noise waveforms on the power supply network. Experimental results show that the worst case switching noise on the power supply network for ISCAS85 benchmark circuits implemented in TSMC 0:25µm technology can be as high as 40% of the supply voltage Vdd.