Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-pad power/ground network design for uniform distribution of ground bounce
DAC '98 Proceedings of the 35th annual Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Thermal placement for high-performance multichip modules
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noise driven in-package decoupling capacitor optimization for power integrity
Proceedings of the 2006 international symposium on Physical design
Heuristic power/ground network and floorplan co-design method
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Power supply noise is strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modules based on their spatial correlations in the floorplan. In this paper, power supply noise is, for the first time, incorporated into the cost function to determine the optimal floorplan in terms of real, wire length, and power supply noise. Compared to the conventional floorplanning which only considers area and wire length, power supply noise aware floorplanning can generate better floorplan both in terms of area and peak noise. The decoupling capacitance required by each module is also calculated and placed in the vicinity of the target module during the floorplanning process. Experimental results on MCNC benchmark circuits show that the peak power supply noise can be reduced as much as 40% and both the total area and wire length are improved due to the reduced total decoupling capacitance budget gained from reduced power supply noise.