System level optimization and design space exploration for low power
Proceedings of the 14th international symposium on Systems synthesis
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Proceedings of the 46th Annual Design Automation Conference
Multi-layer bus minimization for SoC
Journal of Systems and Software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account since the early phases of a complex System-on-Chip design. In this paper some guidelines are provided for the integration of the information on power consumption in the executable model of parameterized cores, with particular attention to the AMBA AHB bus. This will give important information for the analysis and choice between different design architectures driven by functional, timing and power constraints of the System-on-Chip.