An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks

Authors:
Adeoye Olugbon;Sami Khawam;Tughrul Arslan;Ioannis Nousias;Iain Lindsay
Affiliations:
The University of Edinburgh, Scotland;The University of Edinburgh, Scotland;The University of Edinburgh, Scotland;The University of Edinburgh, Scotland;The University of Edinburgh, Scotland
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 4
Cited 3

Power analysis of embedded software: a first step towards software power minimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Advanced Computer Architecture: Parallelism,Scalability,Programmability

Advanced Computer Architecture: Parallelism,Scalability,Programmability
Instrumentation Set-up for Instruction Level Power Modeling

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Integration, the VLSI Journal
High throughput memory data-path design for multi-core architecture

CAR'10 Proceedings of the 2nd international Asia conference on Informatics in control, automation and robotics - Volume 3

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA High-Speed Bus (AHB). The architecture features multiple low-area flyby DMA blocks for transferring configuration data. Furthermore, the architecture eliminates the use of energy-consuming instructions used in comparable commercial reconfigurable SoCs. The flyby DMA blocks achieve a reduction of up to 98% in the number of gates found in general-purpose DMA controllers. The DMA blocks also achieve the flyby throughput which halves the number of clock cycles used in conventional DMA for data transfer. We also demonstrate the presence of parallel processing which contributes to improved system performance of the proposed architecture over commercial comparatives.