Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy estimation for 32-bit microprocessors
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A programmable unified cache architecture for embedded applications
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS)
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Balancing design options with Sherpa
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Requirements for Interfacing IP-Components in Re-configurable Platforms
Journal of VLSI Signal Processing Systems
Application-specific customization of parameterized FPGA soft-core processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Journal of Systems Architecture: the EUROMICRO Journal
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Multi-granularity sampling for simulating concurrent heterogeneous applications
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
Microprocessors & Microsystems
The shape of the processor design space and its implications for early stage explorations
ACMOS'05 Proceedings of the 7th WSEAS international conference on Automatic control, modeling and simulation
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models
Proceedings of the Conference on Design, Automation and Test in Europe
A comparative evaluation of multi-objective exploration algorithms for high-level design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully incorporated our technique into the parameterized SOC tuning environment (Platune) and applied it to a number of applications.