System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A software framework for efficient system-level performance evaluation of embedded systems
Proceedings of the 2003 ACM symposium on Applied computing
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fuzzy decision making in embedded system design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A practical FPGA-based framework for novel CMP research
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
An Automated Design Flow for NoC-based MPSoCs on FPGA
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
A Fast Emulation-Based NoC Prototyping Framework
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
COTSon: infrastructure for full system simulation
ACM SIGOPS Operating Systems Review
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Proceedings of the 47th Design Automation Conference
Dynamically reconfigurable register file for a softcore VLIW processor
Proceedings of the Conference on Design, Automation and Test in Europe
ACM SIGARCH Computer Architecture News
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures
IEEE Embedded Systems Letters
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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.