High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Filtering Memory References to Increase Energy Efficiency
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Data Structures and Algorithms
Data Structures and Algorithms
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decision-theoretic exploration of multiProcessor platforms
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Analysing qos trade-offs in wireless sensor networks
Proceedings of the 10th ACM Symposium on Modeling, analysis, and simulation of wireless and mobile systems
Quality-of-service trade-off analysis for wireless sensor networks
Performance Evaluation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-processor system-on-chip design space exploration based on multi-level modeling techniques
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model-driven design-space exploration for embedded systems: the octopus toolset
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Software energy optimization through fine-grained function-level voltage and frequency scaling
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Towards a model driven refinement process through architecture evaluation
Proceedings of the Fourth International Workshop on Nonfunctional System Properties in Domain Specific Modeling Languages
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models
Proceedings of the Conference on Design, Automation and Test in Europe
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized embedded systems. The exploration problem is multi-objective (e.g., energy and delay), so the main goal of this work is to find a good approximation of the Pareto-optimal configurations representing the best energy/delay trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework to simulate the target system and to dynamically profile the target applications. In the proposed DSE framework, a set of heuristic algorithms have been analyzed to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints. Experimental results, derived from the application of the proposed DSE framework to a superscalar architecture, show that the exploration time can be reduced by three orders of magnitude with respect to the full search approach, while maintaining a good level of accuracy.