Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Artificial Intelligence: A Modern Approach
Artificial Intelligence: A Modern Approach
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Benefits and challenges for platform-based design
Proceedings of the 41st annual Design Automation Conference
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-processor system-on-chip design space exploration based on multi-level modeling techniques
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Boosting design space explorations with existing or automatically learned knowledge
MMB'12/DFT'12 Proceedings of the 16th international GI/ITG conference on Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance
Exploiting domain knowledge in system-level MPSoC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, we present an efficient technique to perform design space exploration of a multi-processor platform that minimizes the number of simulations needed to identify the power-performance approximate Pareto curve. Instead of using semi-random search algorithms (like simulated annealing, tabu search, genetic algorithms, etc.), we use domain knowledge derived from the platform architecture to set-up exploration as a decision problem. Each action in the decision-theoretic framework corresponds to a change in the platform parameters. Simulation is performed only when information about the probability of action outcomes becomes insufficient for a decision. The algorithm has been tested with two multi-media industrial applications, namely an MPEG4 encoder and an Ogg-Vorbis decoder. Results show that the exploration of the number of processors and two-level cache size and policy, can be performed with less than 15 simulations with 95% accuracy, increasing the exploration speed by one order of magnitude when compared to traditional operation research techniques.