Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Fast cache and bus power estimation for parameterized system-on-a-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A programmable unified cache architecture for embedded applications
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A system-level methodology for fast multi-objective design space exploration
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Modeling methodology for integrated simulation of embedded systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 2004 ACM symposium on Applied computing
Automatic Tuning of Two-Level Caches to Embedded Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Fast configurable-cache tuning with a unified second-level cache
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Resource mapping and scheduling for heterogeneous network processor systems
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Efficient design space exploration of high performance embedded out-of-order processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design space exploration using time and resource duality with the ant colony optimization
Proceedings of the 43rd annual Design Automation Conference
Decision-theoretic exploration of multiProcessor platforms
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Application-specific customization of parameterized FPGA soft-core processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
Genetic algorithms for hardware-software partitioning and optimal resource allocation
Journal of Systems Architecture: the EUROMICRO Journal
A one-shot configurable-cache tuner for improved energy and performance
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic cache tuning for energy-efficiency using local regression modeling
Proceedings of the 44th annual Design Automation Conference
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems
ACM Transactions on Architecture and Code Optimization (TACO)
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Synthesis of reconfigurable high-performance multicore systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Architecting dependable systems IV
SDL/virtual prototype co-design for rapid architectural exploration of a mobile phone platform
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An ESL approach for energy consumption analysis of cache memories in SoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
Fast configurable-cache tuning with a unified second-level cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space navigation for neighboring power-performance efficient microprocessor configurations
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
ACM Transactions on Embedded Computing Systems (TECS)
A case for visualization-integrated system-level design space exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Heuristic for two-level cache hierarchy exploration considering energy consumption and performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Elastic computing: A portable optimization framework for hybrid computers
Parallel Computing
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
Combining code reordering and cache configuration
ACM Transactions on Embedded Computing Systems (TECS)
Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC
Journal of Systems Architecture: the EUROMICRO Journal
A system-level infrastructure for multidimensional MP-SoC design space co-exploration
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
A comparative evaluation of multi-objective exploration algorithms for high-level design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this work, we provide a technique for efficiently exploring a parameterized system-on-a-chip (SoC) architecture to find all Pareto-optimal configurations in a multi-objective design space. Globally, our approach uses a parameter dependency model of our target parameterized SoC architecture to extensively prune non-optimal sub-spaces. Locally, our approach applies Genetic Algorithms (GAs) to discover Pareto-optimal configurations within the remaining design points. The computed Pareto-optimal configurations will represent the range of performance (e.g., timing and power) tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the parameterized SoC architecture. We have successfully applied our technique to explore Pareto-optimal configurations for a number of applications mapped on a parameterized SoC architecture.