Heuristic for two-level cache hierarchy exploration considering energy consumption and performance

Authors:
A. G. Silva-Filho;F. R. Cordeiro;R. E. Sant'Anna;M. E. Lima
Affiliations:
Department of Computational Systems, University of Pernambuco (UPE), Recife, PE, Brazil;Department of Computational Systems, University of Pernambuco (UPE), Recife, PE, Brazil;Informatics Center, Federal University of Pernambuco (UFPE), Recife, PE, Brazil;Informatics Center, Federal University of Pernambuco (UFPE), Recife, PE, Brazil
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (Two-level Cache Exploration Heuristicconsidering CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used.