A methodology for tuning two-level cache hierarchy considering energy and performance

Authors:
A. G. Silva-Filho;C. C. Araújo
Affiliations:
Federal University of Pernambuco (UFPE), Recife - PE, Brazil;Federal University of Pernambuco (UFPE), Recife - PE, Brazil
Venue:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Year:
2009

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Abstract

In this paper we propose a hybrid methodology for tuning both instruction and data cache configurations in a two-level memory hierarchy. The method aims to minimize energy consumption without compromise the performance. It combines two optimization mechanisms in order improve energy and performance results without increasing the configuration space. Experiments based on simulations were performed for 12 applications from the Mibench suite benchmark and the proposed methodology achieved better efficiency in 60% of the evaluated cases compared with existing heuristics.