A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Automatic Tuning of Two-Level Caches to Embedded Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A first look at the interplay of code reordering and configurable caches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Energy aware memory architecture configuration
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Automatic cache tuning for energy-efficiency using local regression modeling
Proceedings of the 44th annual Design Automation Conference
A methodology for tuning two-level cache hierarchy considering energy and performance
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A combined optimization method for tuning two-level memory hierarchy considering energy consumption
EURASIP Journal on Embedded Systems
An ESL approach for energy consumption analysis of cache memories in SoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
Cache-tuning-aware scratchpad allocation from binaries
Proceedings of the 24th symposium on Integrated circuits and systems design
Heuristic for two-level cache hierarchy exploration considering energy consumption and performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Combining code reordering and cache configuration
ACM Transactions on Embedded Computing Systems (TECS)
Adaptive loop caching using lightweight runtime control flow analysis
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC
Journal of Systems Architecture: the EUROMICRO Journal
An analytical approach for fast and accurate design space exploration of instruction caches
ACM Transactions on Embedded Computing Systems (TECS)
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We describe cache architecture, intended for prototype-orientedIC platforms, that automatically finds the best cacheconfiguration for a particular application. The cache itself canbe configured with respect to the total size, associativity, linesize, and way prediction. The cache architecture includes anexplorer component that efficiently searches the large space ofpossible configurations for the set of points representingmeaningful tradeoffs between performance and energy - thePareto-optimal set. We provide results of experiments showingthat the architecture effectively finds a good set of Pareto pointsfor numerous Powerstone and MediaBench embedded systembenchmarks. Our architecture eliminates the need fortime-consuming simulations to determine the best cacheconfiguration, and imposes little power overhead andreasonable size overhead.