MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
An Integrated Design Environment for Application Specific Integrated Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Challenges for architectural level power modeling
Power aware computing
Cache Configuration Exploration on Prototyping Platforms
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Proceedings of the 2004 ACM symposium on Applied computing
Automatic Tuning of Two-Level Caches to Embedded Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cache Optimization For Embedded Processor Cores: An Analytical Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Fast configurable-cache tuning with a unified second-level cache
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Configurable cache subsetting for fast cache tuning
Proceedings of the 43rd annual Design Automation Conference
Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Building ASIPs: The Mescal Methodology
Building ASIPs: The Mescal Methodology
Methods of inference and learning for performance modeling of parallel applications
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Configuration of an application-specific instruction-set processor (ASIP) through an exhaustive search of the design space is computationally prohibitive. We propose a novel algorithm that models the design space using local regressions. With only a small subset of the design space sampled, our model uses statistical inference to estimate all remaining points. We used our approach to tune a two-level cache with 19,278 legal configurations. Only 1% of the design space was simulated resulting in a 100x speedup over a brute-force approach. In doing so, we were able to identify near optimal configurations for most benchmarks and reduce the overall power of the processor by 13.9% on average, with one benchmark as high as 53%.