MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Cache Configuration Exploration on Prototyping Platforms
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Cache Optimization For Embedded Processor Cores: An Analytical Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A first look at the interplay of code reordering and configurable caches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast configurable-cache tuning with a unified second-level cache
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Automated data cache placement for embedded VLIW ASIPs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy aware memory architecture configuration
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Configurable cache subsetting for fast cache tuning
Proceedings of the 43rd annual Design Automation Conference
Reconfigurable split data caches: a novel scheme for embedded systems
Proceedings of the 2007 ACM symposium on Applied computing
A one-shot configurable-cache tuner for improved energy and performance
Proceedings of the conference on Design, automation and test in Europe
Automatic cache tuning for energy-efficiency using local regression modeling
Proceedings of the 44th annual Design Automation Conference
Tiny split data-caches make big performance impact for embedded applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
A methodology for tuning two-level cache hierarchy considering energy and performance
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A combined optimization method for tuning two-level memory hierarchy considering energy consumption
EURASIP Journal on Embedded Systems
An ESL approach for energy consumption analysis of cache memories in SoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
On the interplay of loop caching, code compression, and cache configuration
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Tag overflow buffering: reducing total memory energy by reduced-tag matching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast configurable-cache tuning with a unified second-level cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flux caches: what are they and are they useful?
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Heuristic for two-level cache hierarchy exploration considering energy consumption and performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Dynamic Cache Reconfiguration for Soft Real-Time Systems
ACM Transactions on Embedded Computing Systems (TECS)
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
TSV: A novel energy efficient Memory Integrity Verification scheme for embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC
Journal of Systems Architecture: the EUROMICRO Journal
Thread-criticality aware dynamic cache reconfiguration in multi-core system
Proceedings of the International Conference on Computer-Aided Design
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The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimizations. We present an automated method for tuning two-level caches to embedded applications for reduced energy consumption. The method is applicable to both a simulation-based exploration environment and a hardware-based system prototyping environment. We introduce the two-level cache tuner, or TCaT - a heuristic for searching the huge solution space of possible configurations. The heuristic interlaces the exploration of the two cache levels and searches the various cache parameters in a specific order based on their impact on energy. We show the integrity of our heuristic across multiple memory configurations and even in the presence of hardware/software partitioning -- a common optimization capable of achieving significant speedups and/or reduced energy consumption. We apply our exploration heuristic to a large set of embedded applications. Our experiments demonstrate the efficacy of our heuristic: on average the heuristic examines only 7% of the possible cache configurations, but results in cache sub-system energy savings of 53%, only 1% more than the optimal cache configuration. In addition, the configured cache achieves an average speedup of 30% over the base cache configuration due to tuning of cache line size to the application's needs.