Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Cache Configuration Exploration on Prototyping Platforms
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Fast instruction cache analysis via static cache simulation
SS '95 Proceedings of the 28th Annual Simulation Symposium
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications
Proceedings of the conference on Design, automation and test in Europe
Automatic Tuning of Two-Level Caches to Embedded Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Integrated Computer-Aided Engineering
Heuristic for two-level cache hierarchy exploration considering energy consumption and performance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Normalized partial distortion search algorithm for block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A fast hierarchical motion vector estimation algorithm using mean pyramid
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
A typical design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. The main goal of an estimation methodology, introduced in this paper, is to provide fast and accurate estimates of the instruction cache miss rate of data-intensive applications implemented on a programmable embedded platform with multi-level instruction cache memory hierarchy, during the early design phases. Information is extracted from both the high-level code description (C code) of the application and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a novel software tool named m-FICA implements the proposed methodology. The miss rate of two-level instruction cache can be estimated with high accuracy (95%), comparing with simulationbased results while the required time cost is much smaller (orders of magnitude) than the simulation-based approaches.