Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Control Flow Driven Splitting of Loop Nests at the Source Code Level
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer
Microprocessors & Microsystems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems
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This paper focuses on I-cache behaviourenhancement through the application of high-levelcode transformations. Specifically, a flow for theiterative application of the I-Cache performanceoptimizing transformations is proposed. Theprocedure of applying transformation is driven by aset of analytical equations, which receive parametersrelated to code and I-cache structure and predict thenumber of I-cache misses. Experimental results froma real-life demonstration application shows thatorder of magnitude reductions of the number of I-cachemisses can be achieved by the application ofthe proposed methodology.