Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Real time aspects of cluster based caches
RTCSA '95 Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
Automatic generation of peephole optimizations
ACM SIGPLAN Notices - Best of PLDI 1979-1999
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Introduces a new method for instruction cache analysis that outperforms conventional trace-driven methods. The new method, static cache simulation, analyzes a program for a given cache configuration and determines prior to execution time if an instruction reference will always result in a cache hit or miss. At run time, counters are incremented to provide the execution frequency of portions of code. In addition, the cache behavior is simulated for references that could not be predicted statically. The dynamic simulation employs a novel view of the cache by updating local state information associated with code portions. The total number of cache hits and misses can be inferred from the frequency counters at program exit. Measurements taken from a variety of programs show that this new method speeds up cache analysis over conventional trace-driven methods by almost an order of a magnitude. Thus, cache analysis with static cache simulation makes it possible do analyze the instruction cache behavior of longer and more realistic program executions.