Flux caches: what are they and are they useful?

Authors:
Georgi N. Gaydadjiev;Stamatis Vassiliadis
Affiliations:
Computer Engineering, EEMCS, TU Delft, The Netherlands;Computer Engineering, EEMCS, TU Delft, The Netherlands
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

Citing 12
Cited 1

A case for two-way skewed-associative caches

ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches

ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Adapting cache line size to application behavior

ICS '99 Proceedings of the 13th international conference on Supercomputing
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Reconfigurable caches and their application to media processing

Proceedings of the 27th annual international symposium on Computer architecture
Cache Memories

ACM Computing Surveys (CSUR)
The MOLEN rho-mu-Coded Processor

FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A New FPGA Architecture for Word-Oriented Datapaths

FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Energy Benefits of a Configurable Line Size Cache for Embedded Systems

ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Automatic Tuning of Two-Level Caches to Embedded Applications

Proceedings of the conference on Design, automation and test in Europe - Volume 1
The MOLEN Polymorphic Processor

IEEE Transactions on Computers

SAD prefetching for MPEG4 using flux caches

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to the traditional approaches, processors designed with flux caches instead of assuming a hardwired cache organization change their cache ”design” on program demand. Consequently program (data and instruction) dynamic behavior determines the cache hardware design. Experimental results to confirm the flux caches potential are also presented.