A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
A Self-Tuning Cache Architecture for Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A self-tuning cache architecture for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Automated data cache placement for embedded VLIW ASIPs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting soft redundancy for error-resilient on-chip memory design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reconfigurable split data caches: a novel scheme for embedded systems
Proceedings of the 2007 ACM symposium on Applied computing
Increasing cache capacity through word filtering
Proceedings of the 21st annual international conference on Supercomputing
Reducing cache energy consumption by tag encoding in embedded processors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Tiny split data-caches make big performance impact for embedded applications
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Flux caches: what are they and are they useful?
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Previous work has shown that cache line sizes impactperformance differently for different desktop programs -some programs work better with small line sizes, otherswith arger line sizes. Typical processors come with aline size that is a compromise, working best on theaverage for a variety of programs. We analyze theenergy impact of different line sizes, for 19 embeddedsystem benchmarks, and we show that tuning the linesize to a particular program can reduce memory accessenergy by 50% in some examples. Our data arguesstrongly for the need for embedded microprocessors tohave configurable line size caches, and for embeddedsystem designers to put effort into choosing the best linesize for their programs.