The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Way-predicting set-associative cache for high performance and low energy consumption
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
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ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Low cost instruction cache designs for tag comparison elimination
Proceedings of the 2003 international symposium on Low power electronics and design
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Proceedings of the 2003 international symposium on Low power electronics and design
Design and analysis of low-power cache using two-level filter scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Self-Tuning Cache Architecture for Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction
Proceedings of the 2004 international symposium on Low power electronics and design
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Way-Halting Cache for Low-Energy High-Performance Systems
IEEE Computer Architecture Letters
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WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A tagless cache design for power saving in embedded systems
The Journal of Supercomputing
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This paper presents a new technique eliminating redundant cache tag and data accesses to reduce energy consumption. We assign a register to each tag in a cache to represent its state. Before starting an access, we can check the tag states in the target cache set to determine which way(s) should be accessed and which should not. Through this method, almost all the accesses in the I-cache can be directed to the target cache way immediately for most benchmark programs. For a 2-way set-associative cache, the energy consumption can be reduced by 76.6% compared with conventional cache architecture, and by 39.8% compared with Block Buffering, a simple but well-known technique. Besides, this approach does not require any special circuitry internal to the cache RAM such as row or column activation mechanisms. This is considered an important advantage in industry because of its easy implementation.