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Caches usually consume a significant amount of energy in modern microprocessors (e.g. superpipelined or superscalar processors). In this paper, we examine contemporary cache design techniques and provide an analytical model for estimating cache energy consumption. We also present several novel techniques for designing energy-efficient caches, which include block buffering, cache sub-banking, and Gray code addressing. Experimental results suggest that both the block buffering and Gray code addressing techniques are ideal for instruction cache designs which tend to be accessed in a consecutive sequence. Cache sub-banking is ideal for both instruction and data caches. Overall, these techniques can achieve an order of magnitude energy reduction on caches.