Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors

  • Authors:

  • B. V. N. Silpa;Anjul Patney;Tushar Krishna;Preeti Ranjan Panda;G. S. Visweswaran

  • Affiliations:

  • Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India;Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India;Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India;Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India;Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India

  • Venue:
  • Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
  • Year:
  • 2008

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Abstract

With increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. Among the different steps in the graphics processing pipeline, we have observed that memory accesses during texture mapping -- a highly memory intensive phase - contribute 30-40% of the energy consumed in typical embedded graphics processors. This makes the texture mapping subsystem an attractive candidate for energy optimization. We argue that a standard cache hierarchy, commonly used by researchers and commercial graphics processors for texture mapping, is wasteful of energy, and propose the Texture Filter Memory, an energy efficient architecture that exploits locality and the relatively high degree of predictability in texture memory access patterns. Our architecture consumes 75% lesser energy for texturing in a fixed function pipeline, incurring no performance overhead and a small area overhead over conventional texture mapping hardware.