Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline

Authors:
K. P. Acken;M. J. Irwin;R. M. Owens;A. K. Garga
Affiliations:
-;-;-;-
Venue:
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Year:
1996

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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract

Scientific visualization and virtual reality have pushed three-dimensional graphics engines to their limits for updating scenes in real-time. One bottleneck of graphic systems is the transformation of an object's vertices into normalized space based on an evaluated transformation stack. This operation as often done in floating point, requiring a fast floating point multiply-accumulate unit. This paper presents architectural optimizations to a graphics pipeline floating point multiply-accumulate unit by using block floating point and parallelism to bypass or merge trivial operations in the matrix multiplications.