Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient support of parallel sparse computation for array intrinsic functions of Fortran 90
ICS '98 Proceedings of the 12th international conference on Supercomputing
A function-composition approach to synthesize Fortran 90 array operations
Journal of Parallel and Distributed Computing
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Probabilistic Inference Schemes for Sparsity Structures of Fortran 90 Array Intrinsics
ICPP '02 Proceedings of the 2001 International Conference on Parallel Processing
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cache designs for energy efficiency
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Dynamic Power Management for Microprocessors: A Case Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Interprocedural Probabilistic Pointer Analysis
IEEE Transactions on Parallel and Distributed Systems
Power optimization of variable-voltage core-based systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
Efficient and scalable compiler-directed energy optimization for realtime applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Journal of Supercomputing
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch
Journal of Signal Processing Systems
Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors
Journal of Systems and Software
Copy propagation optimizations for VLIW DSP processors with distributed register files
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Compiler-directed leakage reduction in embedded microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Power aware SID-based simulator for embedded multicore DSP subsystems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Architecture and Code Optimization (TACO)
Power-Aware instruction scheduling
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Proceedings of the International Conference on Computer-Aided Design
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Energy-aware code motion for GPU shader processors
ACM Transactions on Embedded Computing Systems (TECS)
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Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in microprocessors. This has lead to interest in using architecture and compiler optimization to reduce leakage power (also known as static power) in microprocessors. In this article, we investigate compiler-analysis techniques that are related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating at the component level. Our compiler provides an analysis framework for utilizing instructions to reduce the leakage power. We present a framework for analyzing data flow for estimating the component activities at fixed points of programs whilst considering pipeline architectures. We also provide equations that can be used by the compiler to determine whether employing power-gating instructions in given program blocks will reduce the total energy requirements. As the duration of power gating on components when executing given program routines is related to the number and complexity of program branches, we propose a set of scheduling policies and evaluate their effectiveness. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing leakage power in microprocessors.