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A static power model for architects
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NetBench: a benchmarking suite for network processors
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Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage power modeling and reduction with data retention
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing static leakage energy in microprocessor functional units
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Low cost instruction cache designs for tag comparison elimination
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Fixed Priority Scheduling for Reducing Overall Energy on Variable Voltage Processors
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register allocation for software pipelined multi-dimensional loops
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Compiler-assisted leakage energy optimization for clustered VLIW architectures
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
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RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
System-wide energy minimization for real-time tasks: lower bound and approximation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
IEEE Transactions on Computers
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors
RTCSA '07 Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-wide energy minimization for real-time tasks: Lower bound and approximation
ACM Transactions on Embedded Computing Systems (TECS)
Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs
Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the conference on Design, automation and test in Europe
Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Energy-aware register file re-partitioning for clustered VLIW architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Systems and Software
Loop Transforming for Reducing Data Alignment on Multi-Core SIMD Processors
Journal of Signal Processing Systems
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As feature size shrinks, leakage energy consumption has become an important concern. In this paper, we develop a compiler-assisted instruction-level scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. In the proposed technique, we obtain the schedule with minimum leakage energy from the ones that are generated by repeatedly regrouping a loop based on rotation scheduling and bipartite-matching. We conduct experiments on a set of benchmarks from DSPstone, Mediabench, Netbench, and MiBench based on the power model of the VLIW processors. The results show that our algorithm can achieve significant leakage energy saving compared with the previous work.