Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Transition-overhead-aware voltage scheduling for fixed-priority real-time systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
IEEE Transactions on Computers
Energy efficient DVS schedule for fixed-priority real-time systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
System-wide energy minimization for real-time tasks: Lower bound and approximation
ACM Transactions on Embedded Computing Systems (TECS)
Reactive speed control in temperature-constrained real-time systems
Real-Time Systems
Procrastination Scheduling for Fixed-Priority Tasks with Preemption Thresholds
NPC '08 Proceedings of the IFIP International Conference on Network and Parallel Computing
Minimizing CPU energy in real-time systems with discrete speed management
ACM Transactions on Embedded Computing Systems (TECS)
Leakage-Aware Multiprocessor Scheduling
Journal of Signal Processing Systems
Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors
Journal of Systems and Software
Trade-offs between voltage scaling and processor shutdown for low-energy embedded multiprocessors
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Leakage-aware real-time scheduling for maximal temperature minimization
ACM SIGBED Review - Special Issue on the Work-in-Progress (WIP) Session at the 2009 IEEE Real-Time Systems Symposium (RTSS)
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
High performance dynamic voltage/frequency scaling algorithm for real-time dynamic load management
Journal of Systems and Software
A heuristic energy-aware approach for hard real-time systems on multi-core platforms
Microprocessors & Microsystems
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While Dynamic Voltage Scaling (DVS) is an efficient technique in reducing the dynamic energy consumption of a CMOS processor, methods that employ DVS without considering leakage current are quickly becoming less efficient when considering the processorýs overall energy consumption. A leakage conscious DVS voltage schedule may require the processor to run at a higher-than-necessary speed to execute a given set of real-time tasks, which can result in a large number of idle intervals. To effectively reduce the energy consumption during these idle intervals, and therefore the overall energy consumption, the DVS schedule must judiciously allow the processor to enter and leave the power down state during these idle intervals, while considering the time and energy cost of doing so. In this paper, we present a scheduling technique that can effectively reduce the overall energy consumption for hard real-time systems scheduled according to a fixed priority (FP) scheme. Experimental results demonstrate that a processor using our strategy consumes as less as 15% of the idle energy of a processor employing the conventional strategy.