Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
Thermal-aware post compilation for VLIW architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors
Journal of Systems and Software
A table masking countermeasure for low-energy secure embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power consumption analysis of embedded multimedia application
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
EM analysis of rijndael and ECC on a wireless java-based PDA
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Coupled power and thermal simulation with active cooling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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In this paper, we study leakage power reduction using power gating in the forms of the Virtual power/ground Rails Clamp (VRC) and Multi-threshold CMOS (MTCMOS) techniques. We apply power gating to two circuit types: memory-based units and datapath components. Using a microarchitecture-level power simulator, as well as power and timing models derived from detailed circuit designs, we further study leakage power modeling and reduction at the system level for modern high-performance VLIW processors. We show that the leakage power can be over 40% of the total power for such processors. Moreover, we propose time-out scheduling of VRC to reduce power up to 85.65% for L2 cache. This power savings results in close to 1/3 total power dissipation for the VLIW processors we study.