Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The effectiveness of multiple hardware contexts
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Inter-task register-allocation for static operating systems
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interprocedural Probabilistic Pointer Analysis
IEEE Transactions on Parallel and Distributed Systems
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Copy propagation optimizations for VLIW DSP processors with distributed register files
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Compiler supports and optimizations for PAC VLIW DSP processors
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
pTest: an adaptive testing tool for concurrent software on embedded multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Signal Processing Systems
A run-time task migration scheme for an adjustable issue-slots multi-core processor
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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High-performance and low-power VLIW DSP processors are increasingly being deployed in mobile devices to process video and multimedia applications. The diverse applications of such systems has led to recent research efforts focusing on their resource management and kernel scheduling. In this paper, we address the enhancing the performance of the microkernel for a VLIW DSP processor, called PAC architectures. In order to reduce the number of read and write ports in register files of VLIW architectures, so as to reduce both the power consumption and implementation costs, a distributed register file and multibank register architectures are being adopted in PAC architectures. These methods present challenges for microkernel designs in terms of reducing context switch overhead. In our work, we propose a multiset descriptor mechanism with compiler support to reduce the context switch overheads associated with the use of registers. The experiments were done with the microkernel system called pCore which has an efficient and tiny design that prunes its code size down under 11 Kbytes. Experimental results show that our multiset context-switching mechanism may reduce the context switch overhead up to 30%.