DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
A unified processor architecture for RISC & VLIW DSP
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Concurrency and Computation: Practice & Experience - Current Trends in Compilers for Parallel Computers (CPC2006)
Journal of Signal Processing Systems
Journal of Signal Processing Systems
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch
Journal of Signal Processing Systems
Concurrency and Computation: Practice & Experience - Compilers for Parallel Computers 2007 Workshop (CPC 2007)
Copy propagation optimizations for VLIW DSP processors with distributed register files
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Compiler supports and optimizations for PAC VLIW DSP processors
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
A portable, efficient inter-core communication scheme for embedded multicore platforms
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems
Building a scalable and portable message-passing library for embedded multicore systems
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Compiler supports for VLIW DSP processors with SIMD intrinsics
Concurrency and Computation: Practice & Experience
MCEmu: A Framework for Software Development and Performance Analysis of Multicore Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A real-time, energy-efficient system software suite for heterogeneous multicore platforms
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Queueing model analysis and scheduling strategy for embedded multi-core SoC based on task priority
Computers and Electrical Engineering
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In order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).