Compiler supports and optimizations for PAC VLIW DSP processors

Authors:
Yung-Chia Lin;Chung-Lin Tang;Chung-Ju Wu;Ming-Yu Hung;Yi-Ping You;Ya-Chiao Moo;Sheng-Yuan Chen;Jenq-Kuen Lee
Affiliations:
Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan;Department of Computer Science, National Tsing-Hua University, Hsinchu, Taiwan
Venue:
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
Year:
2005

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Abstract

PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.