A unified processor architecture for RISC & VLIW DSP
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Journal of Signal Processing Systems
A Novel instruction stream buffer for VLIW architectures
Computers and Electrical Engineering
Copy propagation optimizations for VLIW DSP processors with distributed register files
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Compiler supports and optimizations for PAC VLIW DSP processors
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
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The VLIW processors with static instruction scheduling and thusdeterministic execution times are very suitable forhigh-performancereal-time DSP applications. But the two majorweaknesses in VLIW processors prevent the integration ofmorefunctional units (FU) for a higher instruction issuing rate -the dramatically growing complexity in the register file (RF), andthe poor code density. In this paper, we propose a novelring-structure RF, which partitions the centralized RF into 2Nsub-blocks with an explicit N-by-N switch network for N FU. Eachsub-block only requires access ports for a single FU. We alsopropose the hierarchical VLIW encoding with variable-lengthRISC-like instructions and NOP removal. The ring-structure RF saves91.88% silicon area and reduces 77.35% access time of thecentralized RF. Our simulation results show that the proposedinstruction set architecture with the exposed ring-structure RF hascomparable performance with the state-of-the-art DSP processors.Moreover, the hierarchical VLIW encoding can save 32%~50% codesizes.