An Efficient VLIW DSP Architecture for Baseband Processing
ICCD '03 Proceedings of the 21st International Conference on Computer Design
DSP implementation issues for UMTS-channel coding
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
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In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high-speed channel coding sequence generator that can support IEEE802.16 WiMAX and IEEE 802.22 Wireless Regional Area Network (WRAN). The paper focuses on exploiting the binary property of data value and the finite bit-string organization of data on the DSP systems. The impact on parametric variables of the sequence generator on the computational clock-cycles is analyzed. Computational results of sequence generation on TI 'C64x DSP show that the proposed design achieves significant speed improvement over the conventional sequential implementation. With this improvement, more functionalities can be included in a single DSP or lower power consumptions can be expected.