A unified processor architecture for RISC & VLIW DSP

Authors:
Tay-Jyi Lin;Chie-Min Chao;Chia-Hsien Liu;Pi-Chen Hsiao;Shin-Kai Chen;Li-Chun Lin;Chih-Wei Liu;Chein-Wei Jen
Affiliations:
National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan;National Chiao Tung University, Taiwan
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

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Abstract

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.