Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors

Authors:
Chi Wu;Kun-Yuan Hsieh;Yung-Chia Lin;Chung-Ju Wu;Wen-Li Shih;S. C. Chen;Chung-Kai Chen;Chien-Ching Huang;Yi-Ping You;Jenq Kuen Lee
Affiliations:
National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan;National Tsing-Hua University, Taiwan
Venue:
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Year:
2006

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Abstract

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variablelength encodings for instructions, and special data paths are frequently adopted. This creates challenges to deploy software toolkits for new embedded DSP processors. This article presents our methods and experiences to develop software and toolkit flows for PAC (Parallel Architecture Core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger, and DSP micro-kernels. We first retarget Open Research Compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assmeber are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dualcore environments. The footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations.