Parallel Architecture Core (PAC)--the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

  • Authors:

  • Jia-Ming Chen;Chun-Nan Liu;Jen-Kuei Yang;Shau-Yin Tseng;Wei-Kuan Shih;An-Yeu Wu

  • Affiliations:

  • Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan;ICL, Industrial Technology Research Institute, Hsinchu, Taiwan;ICL, Industrial Technology Research Institute, Hsinchu, Taiwan;ICL, Industrial Technology Research Institute, Hsinchu, Taiwan;Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2011

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Abstract

Two representative multimedia applications--AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data- and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for rich-function and resource constraint portable devices.