A survey of process migration mechanisms
ACM SIGOPS Operating Systems Review
A new process migration algorithm
ACM SIGOPS Operating Systems Review
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
A Fast Interrupt Handling Scheme for VLIW Processors
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Selective code/data migration for reducing communication energy in embedded MpSoC architectures
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Assessing task migration impact on embedded soft real-time streaming multimedia applications
EURASIP Journal on Embedded Systems - Operating System Support for Embedded Real-Time Applications
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch
Journal of Signal Processing Systems
Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors
IEEE Transactions on Parallel and Distributed Systems
Push-assisted migration of real-time tasks in multi-core processors
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Customizing the datapath and ISA of soft VLIW processors
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Distributed task migration for thermal management in many-core systems
Proceedings of the 47th Design Automation Conference
Adaptive Task Migration Policies for Thermal Control in MPSoCs
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
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In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor. The processor has four 2-issue ρ-VEX VLIW cores that can be merged together to form larger issue-width cores. With a task migration scheme, a code running on a core can be shifted to a larger or a smaller issue-width core for increasing the performance or reducing the power consumption of the whole system, respectively. All the cores can be utilized in an efficient manner, as a core needed for a specific job can be freed at run-time by shifting its running code to another core. The task migration scheme is realized with the implementation of interrupts on the ρ-VEX cores. The design is implemented in a Xilinx Virtex-6 FPGA. With different benchmarks, we demonstrate that migrating a task running on a smaller issue-width core to a larger issue-width core at run-time results in a considerable performance gain (up to 3.6x). Similarly, gating off one, two, three, or four cores can reduce the dynamic power consumption of the whole system by 24%, 42%, 61%, or 81%, respectively.