A case for two-way skewed-associative caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Skewed Associativity Improves Program Performance and Enhances Predictability
IEEE Transactions on Computers
Cache designs for energy efficiency
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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This paper proposes an efficient cache scheme to reduce power consumption and conflict misses for single-core or multi-core embedded computing architecture. The proposed cache requires an additional gate stage before it accesses the cache line, which allows the use of a buffer to save the last memory reference. Each memory reference can be checked in the buffer before accessing the cache. If the data is in the buffer, the cache access can be aborted to reduce power consumption. Our simulation results show that it can reduce power consumption, access penalty, and cache misses significantly compared to other conventional caches such as direct-mapped and 2-way set-associative.