Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
Automatic Tuning of Two-Level Caches to Embedded Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic Voltage and Cache Reconfiguration for Low Power
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A self-tuning cache architecture for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A first look at the interplay of code reordering and configurable caches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
IEEE Computer Architecture Letters
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A one-shot configurable-cache tuner for improved energy and performance
Proceedings of the conference on Design, automation and test in Europe
Lightweight runtime control flow analysis for adaptive loop caching
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%.