Energy aware memory architecture configuration

Authors:
Hanene Ben Fradj;Asmaa el Ouardighi;Cécile Belleudy;Michel Auguin
Affiliations:
Laboratoire d'Informatique, signaux et Systèmes de Sophia-Antipolis, Sophia-Antipos Cedex, France;Laboratoire d'Informatique, signaux et Systèmes de Sophia-Antipolis, Sophia-Antipos Cedex, France;Laboratoire d'Informatique, signaux et Systèmes de Sophia-Antipolis, Sophia-Antipos Cedex, France;Laboratoire d'Informatique, signaux et Systèmes de Sophia-Antipolis, Sophia-Antipos Cedex, France
Venue:
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Year:
2004

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Abstract

In the context of battery-driven embedded systems, reducing energy while maintaining performance is one of today's challenges. The on-chip memory count for a great part of the whole system consumption, especially for images and video processing applications that make heavy use of large memory data size.In this paper, we present new technique for efficiently exploiting on-chip memory space (cache, scrathpad) for a specific application to reduce the energy consumption without loss of performance. We configure and compare the impact of three different memory architectures on the energy consumption. The first one is composed of main memory with cache, in the second architecture we find a main memory and scratchpad memory and in the last architecture we combine both cache and scratchpad with the main memory. We show the effectiveness of the last architecture and a saving about 35% in energy consumption.