Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ACM Transactions on Computer Systems (TOCS)
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IEEE Design & Test
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IEEE Design & Test
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IEEE Design & Test
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Proceedings of the tenth international symposium on Hardware/software codesign
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EDTC '95 Proceedings of the 1995 European conference on Design and Test
Transaction Level Modeling: Flows and Use Models
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
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Observations on power-efficiency trends in mobile communication devices
EURASIP Journal on Embedded Systems
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Proceedings of the First Workshop on Virtualization in Mobile Computing
Performance analysis of LTE protocol processing on an arm based mobile platform
SOC'09 Proceedings of the 11th international conference on System-on-chip
Optimal resource management for a model driven LTE protocol stack on a multicore platform
Proceedings of the 8th ACM international workshop on Mobility management and wireless access
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In this paper we present a new hardware/software co-design methodology for embedded systems, where software components written in Specification and Description Language (SDL) execute on a soft-model of a hardware platform, a so called Virtual Prototype (VP). The proposed approach enables fast exploration of difierent hardware and software design options at high level of abstraction in order to make early system design decisions. We prove our approach by considering the Long Term Evolution (LTE) communication stack as a use case for the architectural exploration of our mobile terminal. The open source L4/Fiasco microkernel is deployed as a Real-Time OS to run the modem application represented by the LTE SDL-modelled protocol stack. We profile and analyze the system performance by measuring average and maximum packet processing times under various hardware and software conditions. Thereby, we are able to rapidly obtain an eficient design point that provides 80% packet processing speedup against other unoptimized implementations while meeting the required timing constraints and maintaining a good balance between area and power consumption.