Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Efficient Modeling of Preemption in a Virtual Prototype
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Performance Analysis of Embedded Media Applications in Newer ARM Architectures
ICPPW '05 Proceedings of the 2005 International Conference on Parallel Processing Workshops
Proceedings of the conference on Design, automation and test in Europe
Observations on power-efficiency trends in mobile communication devices
EURASIP Journal on Embedded Systems
Acceleration of the L4/Fiasco microkernel using scratchpad memory
Proceedings of the First Workshop on Virtualization in Mobile Computing
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
SDL/virtual prototype co-design for rapid architectural exploration of a mobile phone platform
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Optimal resource management for a model driven LTE protocol stack on a multicore platform
Proceedings of the 8th ACM international workshop on Mobility management and wireless access
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In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly increased computational demands in LTE and future mobile devices. A virtual proto typing approach is adopted in order to simulate a state-of-the-art mobile phone platform which is based on an ARM1176 core. Moreover a physical layer and base station emulator is implemented that allows for protocol investigations on transport block level at different transmission conditions. By simulating LTE data rates of 100 Mbi/s and beyond, we measure the execution times in a protocol stack model which is compliant to 3GPP Rel.8 specifications and comprises the most processing intensive downlink (DL) part of the LTE L2 data plane. We show that the computing power of a single embedded processor at reasonable clock frequencies is not enough to cope with the L2 requirements of next generation mobile devices. Thereby, Robust Header Compression (ROHC) processing is identified as the major time critical software algorithm, demanding half of the entire L2 DL execution time. Finally, we illustrate that a conventional hardware acceleration approach for the encryption algorithms fails to offer the performance required by LTE and future mobile phones.