Improving the cache locality of memory allocation
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Cache-conscious structure layout
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hoard: a scalable memory allocator for multithreaded applications
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Storage Management Programmable Process
Storage Management Programmable Process
Dynamic Storage Allocation: A Survey and Critical Review
IWMM '95 Proceedings of the International Workshop on Memory Management
Improving Cache Behavior of Dynamically Allocated Data Structures
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
A locality-improving dynamic memory allocator
Proceedings of the 2005 workshop on Memory system performance
Systematic dynamic memory management design methodology for reduced memory footprint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory management thread for heap allocation intensive sequential applications
Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture
The LTE/SAE trial initiative: taking LTE/SAE from specification to rollout
IEEE Communications Magazine
Performance analysis of LTE protocol processing on an arm based mobile platform
SOC'09 Proceedings of the 11th international conference on System-on-chip
Modeling LTE protocol for mobile terminals using a formal description technique
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
SDL/virtual prototype co-design for rapid architectural exploration of a mobile phone platform
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Proceedings of the Conference on Design, Automation and Test in Europe
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The Long Term Evolution (LTE) is the successor technology of the 3G wireless system. The high data rates enabled by LTE can benefit from a strong computational power provided by today's high-performance embedded processors. In this work we therefore utilize a multicore processor to increase the LTE system throughput in the mobile terminal. We investigate the dynamic memory allocation scheme for the LTE protocol stack, modeled using Specification and Description Language (SDL), as the underlying issue with migrating from single to multiple cores. We discover that, under some schemes, multicore performance becomes inferior to a single-core, especially in case of intensive dynamic memory allocation and deallocation. By modifying the SDL system's run time kernel we implement a static memory management scheme. This is supplemented by a selective usage of resource protection in single- and dual-core situations. As a result, an increase of the system throughput by about 75% can be observed when migrating from one core to two cores.